Commentary: China DRAM industry set to rise

China's DRAM industry is set to take a big step forward as its state-backed technology conglomerate Tsinghua Unigroup has successfully raided a senior executive from Taiwan's DRAM industry.

Charles Kau, chairman of Inotera Memories and president of Nanya Technology, is expected to join Tsinghua Unigroup soon after leaving his current positions.

Kau will serve as executive VP of Tsinghua Unigroup's global operations, steering the development of China's home-grown DRAM and NAND flash technology and production capacity, as well as the build-up of a competitive talent pool for China's DRAM sector.

While confirming Kao's resignation, Nanya said Kao's new position will be facilitating the future cooperation among cross-strait DRAM industries and Micron Technology. The company is also looking forward to cooperating with Kau to enhance market presence in the Greater China region.

With immense financial strength and government support, Tsinghua Unigroup has recently offered to buy a stake in Micro for US$230 million, an attempt which has been turned down by the US-based DRAM chipmaker.

However, Tsinghua Unigroup's hiring of Kau, chairman of Micron's Taiwan-based subsidiary Inotera Memories, seems to place Kau in a perfect position to renegotiate with Micron for technology cooperation or a eventually tie-up between the two companies.

Given that the DRAM and NAND flash industries have been heading for a downturn recently and the prospects are likely to remain sluggish in 2016, the declining memory chip prices and rising production costs could force Micron to reach some sort of ally agreement with Tsinghua Unigroup.

Some indicate that Micron and Tsinghua Unigroup will build up a 12-inch joint venture fab, with the US-based chipmaker providing DRAM and NAND flash production technologies, while Tsinghua is responsible for building up memory production capacity.

In short, such a 12-inch joint venture fab will serve as a China version of Inotera Memories established by Kau.

Thus, Kau is actually to be in charge of integrating DRAM and NAND flash production capacity in the US, China and Taiwan, enabling Micron to take on Samsung Electronics and SK Hynix, while also helping China to establish its DRAM industry.

IMEC, Cadence tape out first 5nm test chip

Nanoelectronics research center IMEC and EDA company Cadence Design Systems Inc. have announced that they have completed the first tape out of a test chip to be built using a 5nm manufacturing process.

The tape out is aimed at a process that includes both extreme ultraviolet (EUV) lithography as well as 193nm immersion lithography.

There are no active devices in the tape out, which is just back-end-of-line patterning for metal 2 and metal 3 and the cuts, links and via structures between them. The target transistor is a FinFET and the M2 and M3 information is derived from a full processor design, although the front-end-of-line is not included in the tape out.

Place and Route of the M2 layer. Source: IMEC. 

IMEC and Cadence are using a mix of self-aligned quadruple patterning and EUV lithography. Metal pitches were scaled from the nominal 32nm pitch to 24nm pitch to push the limit of patterning. The two parties did not declare which processor was used but such designs are often done with a Cortex-A series processor that is well-characterized at previous node.

he purpose of manufacturing M2 and M3 is to understand the interaction of  patterning, etch, lithography, metallization, power-performance, process window and rule set learning, said Praveen Raghavan, principal engineer at IMEC.

However, during the place and route with Cadence's Innovus tool, a full processor was taken with the device model, parasitics and timing closure. Both the full processor and SRAM were placed in the design but for now the tape out is only M2-via-M3.

The team at IMEC plans to expose the tape out in at least three ways.

1. SAQP for M2 and M3 with 193i for the cuts and vias using multi exposure.

2. SAQP for M2 and M3 with EUV for the cuts and vias using single exposure.

3. EUV for M2, M3 and vias with no cuts.

Semiconductor stocks are hitting a 'key decision point'

Semiconductor stocks were one of the best-performing industry groups in the S&P 500 on Wednesday, rising more than 3 percent.

And according to one technician, the group is approaching a "key decision point" that could lead both semiconductor stocks and the overall market higher.

"They're actually some pretty nice leadership today," Todd Gordon of TradingAnalysis.com said Wednesday on CNBC's "Power Lunch." "You've got pharma, you've got health care, you've got semis leading the way up."

Gordon said the industry group is bouncing off a support line near $545, which it also hit a year ago.

Now, Gordon is looking for the group to break through the recent downtrend since June of this year.

"I just want to trade towards it, and if we break through it, then we can talk about higher prices," Gordon said Wednesday.

One stock in the industry group in particular is a standout, according to Dennis Davitt of Harvest Volatility Advisor.

Davitt said Intel is one of the best bets within semiconductor stocks, partly because of new opportunity in the mobile business and automated driverless cars, which tech giants such as Google and Apple are currently working to develop.

"It's relatively a conservative stock, but it's also moving into growth areas," Davitt said Wednesday. "With all the automatic driving cars out there, Intel is really big in that space. So anything under the hood that involves a chip, is pretty much owned by Intel."

TSMC turns logic FinFET into ReRAM

As nature and engineering usually contrive to make things difficult for engineers this is seemingly a most unusually convenient development. And also potentially an industry-changing development.

The paper is set to show that hafnium-dioxide high-k dielectric material, which is used in the high-k metal gate (HKMG) of a 16nm FinFET, can also be used as a resistive memory device. It is likely that the dielectric is laid down as a separate ReRAM device adjacent to the transistor. The paper comes shortly after Intel and Micron announced a development in non-volatile memory technology dubbed 3D Xpoint (see Intel, Micron launch "bulk-switching" ReRAM). 

However, at IEDM researchers from Taiwan's Tsing-Hua University and foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. are set to report on a 1kbit memory array made using TSMC's 16nm FinFET logic manufacturing process. It is dubbed a FinFET Dielectric memory, or FIND. 

Paper 10.1 is: 1Kbit FinFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process.

Other virtues of the approach are that the FinFET can be used as the select transistor in the array and the dioxide-based resistive dielectric film for a storage node of the ReRAM cell. No additional masks or process steps are required, the paper's abstract states. The ReRAM cell size is 0.07632 square micrometers. This means that the memory, if it can show the desired read, read and endurance performance is intrinsically available as an embedded memory for SoCs. It could even allow a logic process to be used for making discrete memory ICs. 

Hafnium dioxide has been used for many years as the high dielectric constant "insulator" within logic transistors. At the same time as a dielectric material it has also been extensively studied by research institutes such as IMEC and Tsing-Hua University as a transition metal oxide with potential as a two-terminal resistive RAM.

The abstract states that the 1-kbit device shows low-voltage operation, good retention and excellent reliability and concludes that the FIND ReRAM is a promising embedded non-volatile memory for the FinFET era. 

There doesn't appear to be any paper at IEDM on the underlying technology behind the Intel, Micron 3D Xpoint. 


IEDM is scheduled to take place at the Washington D.C. Hilton Hotel from December 7 to 9.

Globalfoundries developing 10nm in-house

Globalfoundries plans to develop 10nm process technology in-house instead of relying on licensing from Samsung, according to industry sources.

In April 2014, Globalfoundries and Samsung jointly announced their collaboration to deliver production capacity for 14nm FinFET process technology, which was developed by Samsung and licensed to Globalfoundries.

Globalfoundries and Samsung have teamed up to successfully grab 14nm chip orders from Apple, Qualcomm and AMD, said the sources. The pair once stood a good chance of obtaining orders from Nvidia, which is still sticking with TSMC for 16nm FinFET production, the sources indicated.

However, Globalfoundries has moved to develop its next-generation 10nm process technology internally, after finding that partnering with Samsung is not quite a cost-effective strategy, the sources observed.

In fact, the partnership between Globalfoundries and Samsung has begun to lose its competitive advantage, the sources said. Though the pair beat TSMC in the 14/16nm FinFET race, TSMC has improved the yield rate of its 16nm FinFET fast and is ramping up the process production quickly. The smooth ramping and stable yield performance could help TSMC win back orders from Qualcomm and AMD, the sources noted.

For Globalfoundries, paying Samsung licensing fees will be more expensive than using IBM's IPs to develop its own technology, the sources suggested. Besides, Globalfoundries recently completed its acquisition of IBM's microelectronics business. The addition of engineering workforce from IBM's chip-manufacturing unit will surely make a positive contribution to Globalfoundries' development of 10nm and more advanced process technologies in-house, the sources said.

Rumors circulated previously that a group of China-based investors supported financially by the government is eyeing Globalfoundries because of the acquisition target's 14nm FinFET technology. But the sources noted that since Globalfoundries' 14nm FinFET technology is licensed by Samsung, the Korea-based vendor would not allow its technology to be sold through such a deal.

IBM Reports Carbon Nanotube Transistor Breakthrough

Perhaps Moore’s law isn’t doomed just yet. Maybe. IBM Research (NYSE: IBM) reported in a paper in Science today a technique for making carbon nanotube transistors with tiny (~9nm) contacts that exhibit low, size-independent resistance. This overcomes a huge hurdle in shrinking transistor size beyond current limits.

“I think this is the first carbon nanotube transistor demonstration with such a small, low resistance contact,” said Shu-Jen Han, manager of the Nanoscale Science & Technology Group at IBM Research and an author on the paper (End-bonded contacts for carbon nanotube transistors with low, size-independent resistance).

“This is critically important for extending Moore’s law,” Han continued. “We all know the carbon nanotube has excellent electrical properties; the carriers move much faster in carbon nanotubes than silicon. That’s why we are all, including IBM, so interested in them. The big challenge has been contact size. I would argue it’s now more important than the channel [in the efforts to shrink transistors].”

Here’s a portion of the paper’s abstract:

“Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub–10-nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors enabling future ultimately scaled device technologies.”

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry. By advancing research of carbon nanotubes to replace traditional silicon, IBM is hoping to pave the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

“These chip innovations are necessary to meet the emerging demands of cloud computing, Internet of Things and Big Data systems,” said Dario Gil, vice president of Science & Technology at IBM Research. “As technology nears the physical limits of silicon, new materials and circuit architectures must be ready to deliver the advanced technologies that will drive the Cognitive Computing era. This breakthrough shows that computer chips made of carbon nanotubes will be able to power systems of the future sooner than the industry expected.”

Sooner than expected doesn’t necessarily mean soon. Han says it may take 10 years or so to flesh out all the problems.

Source: IBM

“This is an important advance but there are many other challenges to be solved such as how to purify the nanotubes, how to place them properly, and we also made good progress there but when we are talking about new technology so many things have to be right. People tend to divide the technology into two parts, materials and the device. Solving the contact size is probably top challenge on the device side. There are still a bunch of issues on the materials side,” said Han.

Indeed the paper points out, “We have only demonstrated p-channel SWNT transistors using p-type end contacts. It will be difficult to form end-bonded n-type contacts to SWNTs in which electrons are directly injected into the conduction band of SWNTs with this carbide formation approach as metals with low enough work function tend to oxidize first rather than react with C. However, it is still possible to realize n-channel SWNT device operation even with end-bonded contacts to high work function metals through electrostatic doping in the vicinity of the source electrode.”

Caveats aside, this is an impressive advance. After decades of processor performance gains, clock rates have stalled in the 3-5GHz range as silicon MOSFETs approach their physical limits. Carbon nanotubes are one of the most promising replacements for silicon in semiconductors. IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology.

“Single-walled carbon nanotubes (SWNTs) potentially offer the optimal performance as the channel material for ultrascaled FETs,” write Han and coauthors, “The SWNT saturation velocity is several times higher than that of Si, and the intrinsic thinness (~1 nm in diameter) of SWNTs provides the superior electrostatic control needed for devices with ultrashort Lch (channel length). Indeed, SWNT transistors with 9 nm Lch outperform the best Si MOSFETs with similar Lch.”

The key obstacle to ultrascaling carbon nanotube transistor technology has been forming low-resistance and scalable contact. The recent work achieves that. Earlier work has relied on so-called side-bonded contacts (conducting metal deposited along the length of the nanotube channel), which exhibited contact-length-dependent resistance behavior – the smaller the contact area, the greater the resistance.

Schematics showing the conversion from a side-bonded contact (left), where the SWNT is partially covered by Mo, to end-bonded contact (right), where the SWNT is attached to the bulk Mo electrode through carbide bonds while the carbon atoms from originally covered portion of the SWNT uniformly diffuse out into the Mo electrode. Source: IBM

IBM Research group overcame the challenge with development of an end-bonded contact in which “the SWNT channel abruptly ends at the metal electrodes through a solid-state reaction between the nanotube and deposited Molybdenum (Mo) electrodes. Although the carrier injection area is limited to a ~2nm2 no barrier was observed for hole transport and resistance remained low.”

“For any advanced transistor technology, the increase in contact resistance due to the decrease in the size of transistors becomes a major performance bottleneck,” said Han. “Our novel approach is to make the contact from the end of the carbon nanotube, which we show does not degrade device performance. This brings us a step closer to the goal of a carbon nanotube technology.”

Besides helping to extend Moore’s law, Han foresees many other interesting applications for carbon nanotube transistors such as the base material for flexible electronics and transparent electronics.

Is Black Phosphorus the New Graphene?

Chemists first synthesized black phosphorus over a hundred years ago. But it was only last year when anybody really took interest in the flaky black stuff. In a series of experiments reported in the first half of 2014, researchers were able to exfoliate black phosphorus into very thin films of only about 10 to 20 atoms thick. Now black phosphorus has become the new darling of two-dimensional materials research and a new hope for a postsilicon world.

The excitement around black phosphorus, which is also called phosphorene in reference to its 2-D cousin graphene, stems mainly from the fact that it has an inherent bandgap, something that graphene lacks. A bandgap, an energy band in which no electron states can exist, is essential for creating the on/off flow of electrons that are needed in digital logic and for the generation of photons for LEDs and lasers.

Black phosphorus doesn’t just have any bandgap. Its bandgap can be fine-tuned by adjusting the number of layers of the material, explains Philip Feng, an assistant professor of electrical engineering and computer science at Case Western Reserve University. His team has demonstrated some of the first black phosphorous mechanical and electronic devices.

The bandgap can be dialed up from 0.3 to 2.0 electron volts. That’s a range covering a regime otherwise unavailable to all other recently discovered 2-D materials. It bridges the bandgaps of graphene (0 eV) and of transition-metal dichalcogenides such as molybdenum disulfide, which range from 1.0 to 2.5 eV.

By combining this bandgap tuning with different choices of contact materials, scientists at Sungkyunkwan University, in South Korea, were recently able to build both n-type transistors—those conducting electrons—and ambipolar transistors, which conduct both holes and electrons. Such a mix brings the material closer to mimicking the complementary logic used in today’s silicon chips.

Scientists are also excited about black phosphorus for photonics, “since optoelectronic functions, including light absorption, emission, and modulation, of semiconductor materials depend on the size of the bandgap,” says Mo Li, a photonics expert at the University of Minnesota. Black phosphorus’s bandgap range means it can absorb and emit light with wavelengths of 0.6 to 4.0 micrometers—covering the visible to infrared. That spectrum could be key to its use in sensors and in optical communications. Li’s group built a black phosphorous photodetector that was able to convert 3 gigabits per second of optical data to electronic signals.

Another cool property, Feng points out, is that black phosphorus possesses an intrinsic, strong in-plane anisotropy, which means its properties are dependent on the direction of the crystal. “This in-plane anisotropy is not readily found in other 2-D crystals derived from layered materials,” he says. His team recently demonstrated the first black phosphorous high-frequency nanoelectromechanical systems resonator. The resonator took advantage of the material’s in-plane anisotropy to generate new elastic behaviors and frequency scaling abilities.

Unfortunately, black phosphorus is hard to make and hard to keep. Currently, it’s made by treating an amorphous form of the element called red phosphorus with high pressure (1 gigapascal) and high temperature (1,000 °C). The resulting millimeter-scale crystals are then exfoliated into atoms-thick flakes for making nanostructures and nanoscale devices.

More troubling is that “when exposed in air, black phosphorous film degrades within a few hours, due to reaction with water vapor and oxygen in air,” explains Li. “Luckily, many inert materials can be used as passivation to preserve black phosphorous devices for weeks or longer.”

If the manufacturing and preservation problems can be solved, perhaps silicon could finally fade to black.

TSMC Preps 10nm, Tunes 16nm. 10nm needs new flow, Xilinx will skip it

SANTA CLARA, Calif. -- TSMC will start early production on a 10nm process this year and 7nm in 2017, executives said in a road map update here. In between, the foundry giant will release a cost-reduced version of its 16nm process next year and a broad portfolio of specialty processes for the Internet of Things, automotive and sensors.

The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What's more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.

In addition, TSMC announced plans for specialty RRAM and MRAM memories that would act as alternatives to embedded flash. It also gave an update on its integrated fan-out (InFO) process, a low cost chip stacking technology that will be in production in 2016 and reportedly will be used in Apple’s next-generation handset, the iPhone 7.

“If anyone will push Moore’s Law to the furthest extent, it will be TSMC,” said Jack Sun, vice president of R&D and chief technologist, speaking at a partner event here.

Sun and colleagues showed a stack of slides about TSMC’s road map but would not provide them to the press or allow photography in the session, attended by several hundred partners and customers. Likewise it would not allow photos of a 10nm FinFET wafer or an InFO wafer with stacked 15mm2 DRAM it showed in a booth on its exhibit floor.

The 10nm ramp “is clearly for a new phone and the candidate is clear,” said Handel Jones, principal of consulting firm IBS, Inc. (Los Gatos).

Mike Demler, an analyst with the Linley Group, attended the event and provided his perspective:

Although the nominal gap in process nodes between Intel and TSMC appears to be narrowing, TSMC is not likely to catch up in terms of actual Moore’s Law scaling any time soon. TSMC’s 16FF+ process delivers only 20nm scaling, so they are still a generation behind Intel’s 14nm in terms of actual die area. TSMC said that 10nm shrinks by 0.52x from 16nm, nearly identical to the 0.53x scaling that Intel achieved from 22nm to 14nm. So if they stay on schedule, in 2017 TSMC will be in production on a 10nm process that is equivalent to the 14nm technology that Intel began producing in 2Q15. At that rate, even though Intel has slipped 10nm to 2H17, they will remain at least a year ahead of TSMC.

TSMC made a working test chip in its 10nm FinFET process, said Sun. The process should deliver a 0.52x area scaling compared to 20nm and support either 18% higher speeds or 40% less power than TSMC’s current leading-edge 16FF+.

The bad news is the 10nm process requires triple patterning and an entire new EDA design flow, said Rahul Deokar, a product management director from Cadence in a separate talk. “There’s an explosion in physical design rules by an order of magnitude,” he said.

The use of colors to delineate separate lithography passes was an option at 20nm, the first node to use two passes through stepers for some layers. At 10nm the use of colors becomes mandatory not only in routing but in placement and extraction tasks as well, he said. Overall, the 10nm process delivers a 10-20% boost in power, performance and area, Deokar said, but was not more specific.

Cliff Hou, vice president for design technology at TSMC was more conservative. He estimated engineers working in the 10nm node will face more than 5,000 design rules compared to 4,000 at 16nm and less than 2,000 in the 28nm node.

TSMC has finished 8,000 standard cell designs in 10nm. It has also validated 10nm minimum voltages in all compilers and voltage ranges from 0.4 to 1.3V. A 56 Gbit/second serdes block should run on 22% less power in 10 than in 16FF+ node, he added.

TSMC has made a working SRAM at 7nm, Sun reported. The node should deliver 40-45% less area and either 10-15% higher speeds or 25-30% lower power than the 10nm node, he said.

The foundry expects to start “risk” production for 7nm in the first quarter of 2017. It is developing the process for existing immersion steppers, Sun told EE Times. Nevertheless, Sun reported progress with EUV systems now running at 90W and expected to have throughput as high as 125 wafers/hour later this year.

TSMC is redesigning its standard cell libraries to deliver 15% higher performance at 7nm compared to existing cells optimized for mobile designs, said Hou. Engineers hope to push performance even further without impacting area, he said.

Meanwhile, the foundry is working on one more fine-tuning step for its first FinFET node. A so-called 16FFC should be available in the middle of 2016  that eliminates as many as ten masks while retaining the same design rules and supporting voltages initially down to .55V and perhaps to 0.4V later.

“Trying to compete with TSMC in FinFETs is getting much tougher,” said analyst Jones of IBS. “The reduction of 10 mask steps means that double patterning has been significantly reduced -- that will reduce costs,” he said.

“One way for TSMC to totally eliminate double patterning at 16nm is to use EUV on some critical layers -- that would be really disruptive, and EUV is getting closer and could be a possibility in 2017 for production,” he added.

TSMC will have its basic IP libraries for the 16FFC process ready by the end of this year. Specialty libraries for automotive ADAS and infotainment chips will come next year.

Indications are TSMC has been slow off the mark with 16nm, it's first FinFET process. It has 25 tapeouts and more than 50 total expected by the end of the year, but no announced 16nm products were mentioned at the event. Intel started shipping last year products using its second generation FinFET process, its 14nm node.

Xilinx was one of the early 16nm TSMC tapeouts but migrated its design to TSMC’s 16FF+ process and has not shipped it yet, a move others are expected to follow. Victor Peng, general manager of products at Xilinx, showed a 5.2 billion transistor Zynq part with four ARM A53 cores, a Mali GPU and H.265 codec that it taped out in the 16+ process.

Xilinx will also deliver a high-end Virtex FPGA in the 16FF+ process. Although Xilinx has built parts in each of TSMC’s last three nodes, it will skip its 10nm process and wait for the 7nm node, Peng said.

In an effort to cover the waterfront of hot opportunities in IoT, automotive and other areas, TSMC showed several waves of specialty process it is now running or developing. They include ultra-low power versions of 55, 40 and 28nm processes debuting this year, a variant of its 16FFC next year and a possible 40nm process supporting 0.6V supplies in 2017.

The 55 and 40nm nodes target wireless microcontrollers and sensor hubs. The 16FFC variant should run at frequencies above a GHz, “certainly enough for high-end wearables,” said Sun.

The ULP nodes reduce supply voltages, extend Vt and sport SRAMs optimized for low leakage. Separately, TSMC will extend its processes for CMOS image sensors to include support for near-infrared imagers next year. In addition, it will expand its capabilities in CMOS MEMS to include MEMS microphones, gas and biometric sensors.

For car makers, the foundry plans a broad array of offerings possibly extending to 600V GaN and 2.5V 28nm nodes in 2019. Meanwhile it expects to support ADAS chips in its 20 and 16nm nodes by the end of next year. A 55nm embedded flash for car makers will be ready this year with a 40nm version supporting 1.5-2.5V operation coming in 2017.

TSMC is also working on specialty memories. An eRRAM device has been demonstrated supporting 100,000 write/erase cycles as an alternative to embedded flash. A 28nm eMRAM sing spin-torque transfer technology could be ready in late 2017 as another alternative.

In chip stacks, TSMC plans to be in production with InFO in 2017. It is suitable for integrating DRAM with cost-sensitive mobile and consumer chips on devices with less than 3,000 pins. One analyst said it will provide significantly more bandwidth and less power than today’s stacks that use wire bonding or flip chip packages.

InFO comes in two versions. One links a logic chip to DRAM memory; another version can stack multiple chips on top of another without a silicon interposer.

The technique requires new design tools such as links that connect separate databases for package and chip designs. Those tols should be ready by the end of the year.

FinFET Rollout Slower Than Expected

The foundry business is heating up as some new and large players are entering the 16nm/14nm finFET market. But foundry customers are taking longer than expected to migrate to finFETs amid some technical and cost issues.

On the foundry front, Intel Corp. has been the sole player in finFETs for some time. But now, Samsung and TSMC are entering the hotly contested 16nm/14nm finFET foundry business. And GlobalFoundries will enter the fray later this year.

In general, though, the foundries were originally projected to move into volume production for 16nm/14nm finFETs by the third quarter of 2014, according to Gartner. “Compared to the schedule we know today, it seems that all suppliers have experienced two to four quarters of delays in 16nm/14nm finFETs,” said Samuel Wang, an analyst with Gartner.

As it turns out, finFETs are harder to master than previously expected. For some time, the foundries have been wrestling with new multi-patterning flows and nagging yield issues with finFETs. And the various and different backend interconnect schemes from the foundries have created some confusion in the market.

Case in point: Intel moved into 14nm finFET production late last year, which was six or so months later than expected. Intel blamed the delay on yield issues. As a result, Intel’s big foundry customer, Altera, has pushed out the production date of its 14nm-based FPGAs from 2014 to late 2015.

More recently, Intel and the other foundries have solved some, if not all, of the manufacturing issues with finFETs. But the delays have pushed out the production schedules of other foundry customers in the finFET arena. Still others, namely Apple and HiSilicon, hope to ramp up finFET-based chips in 2015, but these are the exceptions to the rule. “16nm/14nm should be a high-volume node in 2016,” Wang said.

It’s not just the foundries that are causing the delays, though. Chipmakers have had to change their design methodologies to account for double patterning at 16nm/14nm. At 20nm, much of the coloring of different mask layers was hidden from design teams. That’s no longer true at 16nm/14nm, and it has forced them to make changes in a flow that until these new nodes was a masterful piece of clockwork.

“In the past, you could leave DRC until you were done with the base layer tapeout,” said Sudharkar Jilla, group director for marketing for place and route at Mentor Graphics. “That normally took two weeks. But you can’t leave two weeks to finish DRC and coloring. It’s not possible.”

Process variation has added more delays. The number of corners that need to be addressed has increased, which impacts the schedule for timing closure. There is simply more stuff to consider—four corners is now more like 20 corners, and instead of pin access for one cell there might be five pins per cell, Jilla said. On top of that, design teams must now contend with dynamic power density, which wasn’t an issue at previous nodes. Until now, the big concern has been leakage current. These are not simple subjects to master, even for experienced design teams.

There are other factors at play here, as well. Some customers are sticking with their foundry partners for finFETs, while others are switching camps. Some are dabbling with 16nm/14nm finFETs, but they are waiting for 10nm finFETs. It may take a scorecard to keep track of the changes before the dust settles.

Foundry customers with deep pockets can afford to make the migration to finFETs, but it will cost more money—up to tree times what it costs to design and develop a 28nm planar device. Many other foundry customers can’t afford these costs and will be forced to stay at the 28nm node and above—at least for now. This isn’t all bad news, because there is a sizable IC market that does not require finFETs.

Moreover, with Samsung and TSMC in the finFET mix, foundry customers have some new and competitive options. But most, if not all, foundry customers are still in the same boat and are asking the same question: What are the challenges with finFETs?

Why finFETs?
At the 20nm planar node, the control of the gate becomes problematic in chip designs. Chips, in turn, are running into the so-called short-channel effects.

So at 20nm, chipmakers must migrate from conventional planar processes to finFET transistors at 16nm/14nm and beyond. “The finFET provides much lower power,” said Kelvin Low, senior director of foundry marketing for Samsung. “The channel, where the current flows, is 3D. We had to make it 3D so that the amount of current flowing in the area increases.”

But moving from planar to finFETs is easier said than done. “What has changed is the complexity of product design and technology development,” said Mark Liu, president and co-chief executive of TSMC, at a recent event. “IC design and systems software complexity have demanded the preparation of our design platform much earlier than before. Typically, (it’s) one year earlier than before. As a consequence, new product design requires much larger resources, which translates into higher design costs.”

All told, there are three basic challenges in moving to finFETs—design, manufacturing and cost. On the design front, the big change for foundry customers is the move from a single patterning flow at 28nm and above to a Double Patterning scheme at 20nm and 14nm.

“Designers have been very familiar with planar technology architectures for many generations,” Samsung’s Low said. “For designers, it’s a learning process (with double patterning). In double patterning, we have two masks. You have color A and color B. Designers need to understand how to deal with two colors now, which they have never experienced in the past.”

IC designers will encounter other issues as well. “Even though finFETs get the most publicity, double patterning makes the design flow a little bit more complex,” said Richard Trihy, director of design methodology at GlobalFoundries. “This impacts the entire design flow, such as parasitic extraction and variation. It impacts the implementation tools for place and route. Of course, it impacts DRC, which becomes a more complicated step.”

In response, the foundries and the EDA community are providing new EDA tools and flows to help enable the migration to finFETs. The tools make the migration as transparent as possible for designers, Trihy said.

Chipmakers also face challenges on the manufacturing front. The hard part is to make fins with consistent heights during the etch process. Imprecise fin patterning could cause variations. In addition, finFETs have an assortment of three-dimensional structures that are difficult to measure. Finding killer defects is also problematic.

But perhaps the biggest issue is cost. The average IC design cost for a 28nm device is about $30 million, according to Gartner. In comparison, the IC design cost for a mid-range 14nm SoC is about $80 million. “Add an extra 60% (to that cost) if embedded software development and mask costs are included,” Gartner’s Wang said. “A high-end SoC can be double this amount, and a low-end SoC with re-used IP can be half of the amount.”

On top of that, it takes 100 engineer-years to bring out a 28nm chip design. “Therefore, a team of 50 engineers will need two years to complete the chip design to tape-out. Then, add 9 to 12 months more for prototype manufacturing, testing and qualification before production starts. That is if the first silicon works,” he said. “For a 14nm mid-range SoC, it takes 200 man-years. A team of 50 engineers will need four years of chip design time, plus add nine to 12 months for production.”

If that’s not enough, there is also a sizable jump in manufacturing costs. In a typical 11-metal level process, there are 52 mask steps at 28nm. With an 80% fab utilization rate at 28nm, the loaded manufacturing cost is about $3,500 per 300mm wafer, according to Gartner.

At 1.3 days per lithography layer, the cycle time for a 28nm chip is about 68 days. “Add one week minimum for package testing,” Wang said. “So, the total is two-and-half months from wafer start to chip delivery.”

At 16nm/14nm, there are 66 mask steps. With an 80% fab utilization rate at 16nm/14nm, the loaded cost is about $4,800 per 300mm wafer, according to Gartner. “It takes three months from wafer start to chip delivery,” he added.

Who’s on first?
At 14nm, wafer costs also are going up due to double patterning. Intel, for one, attacked the problem on two fronts. First, it over-scaled the transistor density. Second, it scaled the interconnect pitch by 0.65x, from 80nm at the 22nm node to 52nm at the 14nm node.

In contrast, other foundries combined a 16nm/14nm finFET transistor with a 20nm planar backend. “If you take a look at what others are doing, they chose not to scale the area, which just kills their cost,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.

At 22nm, Intel’s finFET technology has a fin pitch of 60nm and a fin height of 34nm. At 14nm, the fin pitch and height are both 42nm. Intel also went to thinner and taller fins, which are rectangular in shape. “That improves the electrostatics of the fins,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel.

At one time, Intel had a two- to three-year lead in finFETs. But the company’s delays at 14nm are giving its foundry rivals time to close the gap.

Last year, though, TSMC disclosed it would experience share losses in finFETs in 2015. TSMC decided to focus on 20nm in 2015 and finFETs in 2016. In contrast, Samsung basically skipped 20nm to focus on finFETs in 2015, thereby getting the upper hand in the market.

In fact, Samsung entered the finFET market in February by rolling out a chip based on the process. The chip, dubbed the Exynos 7420, is a 64-bit, eight-core SoC. It is based on an 11-metal level process and includes a high-k/metal-gate technology, according to TechInsights. The gate length is about 30nm, with a 77nm contacted gate pitch, according to the firm.

As part of the chip introduction, Samsung also entered the 16nm/14nm finFET foundry market. “We have declared that 14nm is in mass production,” Samsung’s Low said. “We are now seeing a change. What is apparent is there is now a true choice for customers of finFETs.”

Samsung is also ramping up its capacity for foundry customers. In fact, for the next iPhone, Apple has selected Samsung over TSMC for a large percentage of its chips based on 14nm finFETs, according to Pacific Crest Securities.

Today, Samsung has roughly 11,000 wafer starts per month (wspm) of 14nm capacity, which represents about 10% of its total 300mm fab capacity, according to Pacific Crest Securities. Over time, Samsung is expected to convert some of its 28nm capacity, giving it a total of 46,000 wspm of 14nm capacity, according to the firm.

Another foundry vendor, GlobalFoundries, licensed Samsung’s 14nm finFET process some time ago. In its New York fab, GlobalFoudries is capable of ramping up around 30,000 wspm of 14nm finFET capacity, according to Pacific Crest Securities. Later this year, GlobalFoundries will move into finFET production.

Not to be outdone, TSMC will begin volume production for its 16nm finFET process by the middle of this year. By the end of 2016, the company plans to have an installed capacity of 100,000 wspm for 16nm finFET technology, according to J.K. Wang, vice president of 300mm fab operations at TSMC.

TSMC is positioning itself in hopes of regaining share in finFETs. In fact, it’s too early to declare a winner in the finFET foundry business. In many ways, the race has just begun.

Global 2014 semiconductor revenues rise 7.9%, says Gartner

Worldwide semiconductor revenues totaled US$340.3 billion in 2014, a 7.9% increase from 2013 revenues of US$315.4 billion, according to final results by Gartner. The top-25 semiconductor vendors' combined revenues increased 11.7%, which was more than the overall industry's growth.

The world's top-25 semiconductor vendors accounted for 72.4%of total market revenues, up from 69.9% in 2013, said Gartner.

"2014 saw all device categories post positive growth, unlike in 2013, when application-specific integrated circuits (ASIC), discretes and microcomponents all declined. The memory market was the best performer for the second year in a row, growing 16.6%, meaning the rest of the market only achieved 4.9% growth," said Andrew Norwood, research VP at Gartner. "As a group, DRAM vendors performed best, lifted by the booming DRAM market, which saw revenue increase 32% to US$46.1 billion, surpassing the all-time high of US$41.8 billion set in 1995."

Intel saw a return to growth in 2014 after two years of revenue decline, as PC production recovered, with sales up 7.7%, Gartner said. The company retained the number one market share position for the 23rd consecutive year by capturing 15.4% of the market, which was down slightly on the previous year.

2014 saw significantly more merger and acquisition (M&A) activity among the major semiconductor vendors than the previous year, with some announced deals still to close in 2015, Gartner noted. Among the most significant deals was Avago Technologies' acquisition of LSI, propelling the company into the top-25 semiconductor vendors for the first time. MStar Semiconductor was merged with MediaTek after a prolonged merger, and ON Semiconductor acquired Aptina Imaging. After adjusting for closed M&A activity, the top-25 semiconductor vendors grew at 9.1%, Gartner said.

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TSMC to Start 10nm in 2017, Closing Gap with Intel

Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest chip foundry, said that it expects to start 10 nanometer production in 2017, closing the gap with Intel.

“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun said. “Technology-wise, we think we can close the gap at 10nm.”

For the first time this year, TSMC is expected to have the largest capex in the semiconductor industry as it aims to maintain its lead in the foundry business against rivals such as Samsung, Intel and Global Foundries.

TSMC has raised its capital expenditure budget for 2015 to US$11.5-12.0 billion, an increase of 11.5-20.0 percent compared with 2014, mainly due to its confidence in demand for advanced geometries. Intel spent $10.1 billion on capex during 2014. For the current year, Intel expects that figure to hold steady, at $10 billion, plus or minus $500 million.

Few companies can afford the huge investments in advanced production as it getting harder to build ever smaller transistor. Eventually the smaller player will be phase out from the competition and left with bigger players like Intel, TSMC and Samsung.

Intel confident that Moore's Law still valid beyond 10nm

Intel believes that they can still continue to fulfill Moore's Law beyond 10nm with the introduction of new material and device structure, together with close collaboration between their process development and product design teams.

Mark Bohr, an Intel Senior fellow for logic technology development, told the audience during a panel session in International Solid State Circuits Conference that Intel believe the scaling will continue to provide cheaper transistors, but that has to be justified with cost reduction through new process technology.

Bohr even told the audience that he believe Intel can move to 7nm mode without having to resort to EUV lithography. He declined to provide further detail but emphasized that it could be achieve through the use of new material and structures, citing Intel has published papers on III-IV devices.