SANTA CLARA, Calif. -- TSMC will start early production on a 10nm process this year and 7nm in 2017, executives said in a road map update here. In between, the foundry giant will release a cost-reduced version of its 16nm process next year and a broad portfolio of specialty processes for the Internet of Things, automotive and sensors.
The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What's more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.
In addition, TSMC announced plans for specialty RRAM and MRAM memories that would act as alternatives to embedded flash. It also gave an update on its integrated fan-out (InFO) process, a low cost chip stacking technology that will be in production in 2016 and reportedly will be used in Apple’s next-generation handset, the iPhone 7.
“If anyone will push Moore’s Law to the furthest extent, it will be TSMC,” said Jack Sun, vice president of R&D and chief technologist, speaking at a partner event here.
Sun and colleagues showed a stack of slides about TSMC’s road map but would not provide them to the press or allow photography in the session, attended by several hundred partners and customers. Likewise it would not allow photos of a 10nm FinFET wafer or an InFO wafer with stacked 15mm2 DRAM it showed in a booth on its exhibit floor.
The 10nm ramp “is clearly for a new phone and the candidate is clear,” said Handel Jones, principal of consulting firm IBS, Inc. (Los Gatos).
Mike Demler, an analyst with the Linley Group, attended the event and provided his perspective:
Although the nominal gap in process nodes between Intel and TSMC appears to be narrowing, TSMC is not likely to catch up in terms of actual Moore’s Law scaling any time soon. TSMC’s 16FF+ process delivers only 20nm scaling, so they are still a generation behind Intel’s 14nm in terms of actual die area. TSMC said that 10nm shrinks by 0.52x from 16nm, nearly identical to the 0.53x scaling that Intel achieved from 22nm to 14nm. So if they stay on schedule, in 2017 TSMC will be in production on a 10nm process that is equivalent to the 14nm technology that Intel began producing in 2Q15. At that rate, even though Intel has slipped 10nm to 2H17, they will remain at least a year ahead of TSMC.
TSMC made a working test chip in its 10nm FinFET process, said Sun. The process should deliver a 0.52x area scaling compared to 20nm and support either 18% higher speeds or 40% less power than TSMC’s current leading-edge 16FF+.
The bad news is the 10nm process requires triple patterning and an entire new EDA design flow, said Rahul Deokar, a product management director from Cadence in a separate talk. “There’s an explosion in physical design rules by an order of magnitude,” he said.
The use of colors to delineate separate lithography passes was an option at 20nm, the first node to use two passes through stepers for some layers. At 10nm the use of colors becomes mandatory not only in routing but in placement and extraction tasks as well, he said. Overall, the 10nm process delivers a 10-20% boost in power, performance and area, Deokar said, but was not more specific.
Cliff Hou, vice president for design technology at TSMC was more conservative. He estimated engineers working in the 10nm node will face more than 5,000 design rules compared to 4,000 at 16nm and less than 2,000 in the 28nm node.
TSMC has finished 8,000 standard cell designs in 10nm. It has also validated 10nm minimum voltages in all compilers and voltage ranges from 0.4 to 1.3V. A 56 Gbit/second serdes block should run on 22% less power in 10 than in 16FF+ node, he added.
TSMC has made a working SRAM at 7nm, Sun reported. The node should deliver 40-45% less area and either 10-15% higher speeds or 25-30% lower power than the 10nm node, he said.
The foundry expects to start “risk” production for 7nm in the first quarter of 2017. It is developing the process for existing immersion steppers, Sun told EE Times. Nevertheless, Sun reported progress with EUV systems now running at 90W and expected to have throughput as high as 125 wafers/hour later this year.
TSMC is redesigning its standard cell libraries to deliver 15% higher performance at 7nm compared to existing cells optimized for mobile designs, said Hou. Engineers hope to push performance even further without impacting area, he said.
Meanwhile, the foundry is working on one more fine-tuning step for its first FinFET node. A so-called 16FFC should be available in the middle of 2016 that eliminates as many as ten masks while retaining the same design rules and supporting voltages initially down to .55V and perhaps to 0.4V later.
“Trying to compete with TSMC in FinFETs is getting much tougher,” said analyst Jones of IBS. “The reduction of 10 mask steps means that double patterning has been significantly reduced -- that will reduce costs,” he said.
“One way for TSMC to totally eliminate double patterning at 16nm is to use EUV on some critical layers -- that would be really disruptive, and EUV is getting closer and could be a possibility in 2017 for production,” he added.
TSMC will have its basic IP libraries for the 16FFC process ready by the end of this year. Specialty libraries for automotive ADAS and infotainment chips will come next year.
Indications are TSMC has been slow off the mark with 16nm, it's first FinFET process. It has 25 tapeouts and more than 50 total expected by the end of the year, but no announced 16nm products were mentioned at the event. Intel started shipping last year products using its second generation FinFET process, its 14nm node.
Xilinx was one of the early 16nm TSMC tapeouts but migrated its design to TSMC’s 16FF+ process and has not shipped it yet, a move others are expected to follow. Victor Peng, general manager of products at Xilinx, showed a 5.2 billion transistor Zynq part with four ARM A53 cores, a Mali GPU and H.265 codec that it taped out in the 16+ process.
Xilinx will also deliver a high-end Virtex FPGA in the 16FF+ process. Although Xilinx has built parts in each of TSMC’s last three nodes, it will skip its 10nm process and wait for the 7nm node, Peng said.
In an effort to cover the waterfront of hot opportunities in IoT, automotive and other areas, TSMC showed several waves of specialty process it is now running or developing. They include ultra-low power versions of 55, 40 and 28nm processes debuting this year, a variant of its 16FFC next year and a possible 40nm process supporting 0.6V supplies in 2017.
The 55 and 40nm nodes target wireless microcontrollers and sensor hubs. The 16FFC variant should run at frequencies above a GHz, “certainly enough for high-end wearables,” said Sun.
The ULP nodes reduce supply voltages, extend Vt and sport SRAMs optimized for low leakage. Separately, TSMC will extend its processes for CMOS image sensors to include support for near-infrared imagers next year. In addition, it will expand its capabilities in CMOS MEMS to include MEMS microphones, gas and biometric sensors.
For car makers, the foundry plans a broad array of offerings possibly extending to 600V GaN and 2.5V 28nm nodes in 2019. Meanwhile it expects to support ADAS chips in its 20 and 16nm nodes by the end of next year. A 55nm embedded flash for car makers will be ready this year with a 40nm version supporting 1.5-2.5V operation coming in 2017.
TSMC is also working on specialty memories. An eRRAM device has been demonstrated supporting 100,000 write/erase cycles as an alternative to embedded flash. A 28nm eMRAM sing spin-torque transfer technology could be ready in late 2017 as another alternative.
In chip stacks, TSMC plans to be in production with InFO in 2017. It is suitable for integrating DRAM with cost-sensitive mobile and consumer chips on devices with less than 3,000 pins. One analyst said it will provide significantly more bandwidth and less power than today’s stacks that use wire bonding or flip chip packages.
InFO comes in two versions. One links a logic chip to DRAM memory; another version can stack multiple chips on top of another without a silicon interposer.
The technique requires new design tools such as links that connect separate databases for package and chip designs. Those tols should be ready by the end of the year.
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